Getting Started with UVM: A Beginner's Guide

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition

Cracking Digital VLSI Verification Interview: Interview Success

Digital Logic RTL & Verilog Interview Questions

Logic Design and Verification Using SystemVerilog (Revised)

Hands-On Machine Learning with Scikit-Learn and TensorFlow: Concepts, Tools, and Techniques to Build Intelligent Systems

Advanced UVM

Cracking the Coding Interview: 189 Programming Questions and Solutions